There are several applications where a frequency division is needed, for example in frequency generation circuits or frequency synthesizers. Frequency dividers with an even division ratio, for example by two or four, are widely known. In some cases, frequency dividers with an odd division ratio can be needed.
In one existing implementation of a conventional frequency divider with an odd division ratio, a number N of D-flip-flops are cascaded to achieve a division ratio of 2N−1. An input of the first flip-flop is coupled to an output of a NOR-gate having a first input coupled to the output of the first flip-flop and a second input coupled to an output of the N-th flip-flop. Respective clock inputs of the N flip-flops are provided with an input frequency signal. After the N-th flip-flop, an additional flip-flop clocked by the input frequency signal and an AND-gate are provided to perform a synchronization of the divided clock signal. With the synchronization, a balanced duty cycle of about 50% should be achieved.
Logic AND-gates usually have an asymmetry regarding their rise time and fall time as well as their switching from one logic state to another. Furthermore an asymmetry of an AND-gate can be caused by differing switching times between a first and a second input for respective switched logical input signals. If the symmetry in the AND-gate and an input to output delay in the last flip-flop are negligible to a signal period of the input frequency signal, usually a satisfying duty cycle performance can be achieved with a conventional frequency divider. As the signal period of the input frequency signal decreases with an increasing input frequency, the asymmetry of the AND-gate and the delay of the last flip-flop can have a negative influence on the duty cycle performance, depending on the input signal frequency.